1. Field of the Invention
The present invention relates to a semiconductor device and more particularly, to a semiconductor device with repair fuses and redundant circuits and a method of trimming the semiconductor device using a laser beam, which make it possible to save defective semiconductor devices by activating redundant circuits with the use of repair fuses as necessary. The present invention is preferably applied to fabrication of large-capacity semiconductor memory devices equipped with redundant or reserve memory cells.
2. Description of the Related Art
In recent years, large-capacity semiconductor memory devices typically have redundant circuits with reserve memory cells. If some of the memory cells in a semiconductor memory device are found defective in a testing operation, the defective memory cells are identified and replaced with reserve memory cells in the redundant circuits as necessary. Thus, the defect of the semiconductor memory device is repaired; in other words, the semiconductor memory device including the defective memory cells can be saved.
To activate the reserve memory cells in the redundant circuits (i.e., to use the redundant memory cells), after the defective memory cells are identified, they need to be electrically disconnected from the memory cell array and furthermore, the redundant or reserve memory cells need to be electrically connected to the same array instead. Such switching or replacement of electrical connection as explained here is usually realized by mechanically and electrically disconnecting specific wiring lines by way of the repair fuses provided beforehand in the device as necessary.
In the step of repairing the defective memory cell array or saving the defective semiconductor memory device, xe2x80x9credundancy analysisxe2x80x9d is carried out on the basis of test result about whether the individual bit lines and word lines have gotten a pass or fail, thereby identifying the repair fuses to be fused and disconnected. Then, a laser beam is irradiated to the repair fuses thus identified using a laser repair system to disconnect the desired fuses. This step is termed the xe2x80x9claser trimmingxe2x80x9d step.
A method of repairing defective memory cells in a semiconductor memory device using redundant memory cells is briefly explained below.
FIGS. 1 and 2 show a typical configuration of a semiconductor memory device with redundant memory cells and repair fuses.
As shown in FIG. 2, the semiconductor memory device is equipped with a memory cell array 410 including memory cells, a redundant memory cell row 425 that corresponds to a memory cell row of the array 410, and a redundant memory cell column 426 that corresponds to a memory cell column of the array 410. The redundant row and column 425 and 426 are included in a redundant circuit.
Actually, the array 410 includes a large number of memory cells. However, for the sake of simplification of description, the array 410 is illustrated and explained as a 4xc3x974 array, in other words, the array 410 has only four rows and four columns. Also, the following explanation is referred to the redundant memory cell row 425 alone, because the same explanation is applicable to the redundant memory cell column 426.
As shown in FIGS. 1 and 2, the first memory cell row 421 having the Y address of 0 in the array 410 is connected to the output terminal of an AND circuit 431. The second memory cell row 422 having the Y address of 1 in the array 410 is connected to the output terminal of an AND circuit 432. The third memory cell row 423 having the Y address of 2 in the array 410 is connected to the output terminal of an AND circuit 433. The fourth memory cell row 424 having the Y address of 3 in the array 410 is connected to the output terminal of an AND circuit 434.
The rows 421, 422, 423, and, 424 are respectively selected and activated when the output signals B1, B2, B3, and B4 of the AND circuits 431. 432, 433, and 434 have a value of xe2x80x9c0xe2x80x9d, i.e., they are in the state of logic low (L). On the other hand, when the output signals B1, B2, B3, and B4 of the AND circuits 431, 432, 433, and 434 have a value of xe2x80x9c1xe2x80x9d, i.e., they are in the state of logic high (H), the rows 421, 422, 423, and 424 are respectively disconnected from the array 410, i.e., they are inactivated.
The redundant memory cell row 425 is connected to the output terminal of an AND circuit 443. The row 425 is selected and electrically connected to the array 410 (i.e., activated) when the output signal B5 of the circuit 443 has a value of xe2x80x9c1xe2x80x9d.
The AND circuit 431 receives three input signals, i.e., an inverted signal of the selection signal A0, an inverted signal of the selection signal A1, and an inverted signal of the output signal D1 of a NOT circuit 445. Similarly, the AND circuit 432 receives the selection signal A0, the inverted signal of the selection signal A1, and the inverted signal of the output signal D1. The AND circuit 433 receives the inverted signal of the selection signal A0, the selection signal A1, and the inverted signal of the output signal D1. The AND circuit 434 receives the selection signal A0, the selection signal A1, and the inverted signal of the output signal D1.
An input terminal of an Ex-OR (Exclusive Or) circuit 441 receives the selection signal A0 and another input terminal thereof is connected to a terminal of a fuse 451 and a terminal of a resistor 461. The other terminal of the fuse 451 is connected to a power supply line supplied with a power supply voltage Vcc. The other terminal of the resistor 461 is connected to the ground.
An input terminal of an Ex-OR circuit 442 receives the selection signal A1 and another input terminal thereof is connected to a terminal of a fuse 452 and a terminal of a resistor 462. The other terminal of the fuse 452 is connected to the power supply line of Vcc. The other terminal of the resistor 462 is connected to the ground.
An input terminal of a NOT circuit 444 is connected to a terminal of a fuse 453 and a terminal of a resistor 463. The other terminal of the fuse 453 is connected to the power supply line of Vcc. The other terminal of the resistor 463 is connected to the ground.
The AND circuit 443 receives the output signal C1 of the EX-OR circuit 441, and the output signal C2 of the EX-OR circuit 442, and the output signal D2 of the NOT circuit 444. The NOT circuit 445 receives the output signal B5 of the NAD circuit 443.
The semiconductor memory device shown in FIGS. 1 and 2 operates in the following way.
As described above, when the output signal B5 of the AND circuit 443 has a value of xe2x80x9c1xe2x80x9d, the redundant memory cell row 425 is selected and activated. In this case, the output signal D1 of the NOT circuit 445 (i.e., the redundant signal) has a value of xe2x80x9c0xe2x80x9d and therefore, all the AND circuits 431, 432, 433, and 434 receive the signal value of xe2x80x9c1xe2x80x9d. Thus, any one of the output signals B1, B2, B3, and B4 can be set to have a value of xe2x80x9c1xe2x80x9d by changing the combination of the values xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d in the selection signals A0 and A1. This means that any one of the memory cell rows 421, 422, 423, and 424 can be set nonselective, in other words, any one of the rows 421, 422, 423, and 424 can be electrically disconnected from the array 410. At the same time as this disconnection, the redundant row 425 is selected and electrically connected to the array 410 instead.
On the other hand, when the output signal B5 of the AND circuit 443 has a value of xe2x80x9c0xe2x80x9d, the redundant row 425 is not selected. In this case, the output signal D1 of the NOT circuit 445 (i.e., the redundant signal) has a value of xe2x80x9c1xe2x80x9d and therefore, all the AND circuits 431, 432, 433, and 434 receive the signal value of xe2x80x9c0xe2x80x9d. Thus, all the output signals B1, B2, B3, and B4 have a value of xe2x80x9c0xe2x80x9d, which means that all the rows 421, 422, 423, and 424 are selected and activated.
The fuse 453 is fused and cut when the redundant row 425 is selected or activated. The fuse 451 is fused and cut when the selection signal A0 has a value of xe2x80x9c0xe2x80x9d. The fuse 452 is fused and cut when the selection signal A1 has a value of xe2x80x9c0xe2x80x9d.
Here, as shown in FIGS. 1 and 2, it is supposed that the memory cell 427 having the X address of 2 and the Y address of 2 in the memory cell array 410 is defective. In this case, to select the row 423 including the defective cell 427 in the array 410, the values of the selection signals A0 and A1 are set at xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d, respectively. At this time, the fuse 451 is fused and cut since the selection signal A0 has a value of xe2x80x9c0xe2x80x9d. The fuse 453 is fused and cut for selecting and activating the redundant row 425. As a result, the EX-OR circuit 441 and the NOT circuit 444 receive signal values of xe2x80x9c0xe2x80x9d. On the other hand, because the fuse 452 is not cut, the EX-OR circuit 442 receives a signal value of xe2x80x9c1xe2x80x9d.
Accordingly, the output signals C1 and C2 of the EX-OR circuits 441 and 442 have values of xe2x80x9c1xe2x80x9d and the output signal D2 of the NOT circuit 444 has a value of xe2x80x9c1xe2x80x9d. Furthermore, the output signals B5 and B3 of the AND circuits 443 and 433 have values of xe2x80x9c1xe2x80x9d and the output signals B1, B2, and B4 of the AND circuits 441, 442, and 444 have values of xe2x80x9c0xe2x80x9d. Thus, the redundant row 425 is electrically connected to the array 410 and the defective row 423 is electrically disconnected therefrom.
When the selection signal A0 does not have a value of xe2x80x9c0xe2x80x9d and/or the selection signal A1 does not have a value of xe2x80x9c1xe2x80x9d, the redundant row 425 is not selected and activated while none of the rows 421, 422, 423, and 424 are electrically disconnected from the array 410.
The above-described circuit configuration of semiconductor memory devices that makes it possible to activate a redundant cell or cells instead of a defective cell or cells as necessary has been used and is now being used popularly.
Next, the configuration of a prior-art semiconductor device with repair fuses is explained below with reference to FIG. 3.
As shown in FIG. 3, a prior-art semiconductor device 500 is comprised of a semiconductor substrate 501 and repair fuses 550 formed on the substrate 501. The fuses 550 can be fused and cut by irradiating a laser beam from the outside. Actually, several hundreds or thousands of the fuses 550 are provided on the substrate 501. However, only six out of the fuses 550 are illustrated in FIG. 3 for the sake of simplification of explanation.
The fuses 550, which are made of a patterned conductive layer, are arranged on a first dielectric layer (not shown) formed on the surface of the substrate 501. Each of the fuses 550 has a strip-like shape. The fuses 550 are arranged in parallel at the same pitch. Both ends of each fuse 550 are electrically connected to an internal circuit (not shown) of the semiconductor device 500, where the internal circuit has a redundant circuit or circuits.
A second dielectric layer (not shown) is formed on the first dielectric layer to cover all the fuses 550. The second dielectric layer has a function of protecting the fuses 550.
A third dielectric layer (not shown), which has a rectangular opening or window 505, is formed on the second dielectric layer. As shown in FIG. 3, the longitudinal axis of the opening 505 is parallel to the X axis while the strip-shaped fuses 550 extend along the Y axis perpendicular to the X axis. The opening 505 serves as an irradiation window of a laser beam.
The width bxe2x80x2 of each fuse 550 is the same. For example, bxe2x80x2 is set at 1 xcexcm. The pitch axe2x80x2 of the fuses 550 is set to be equal to the sum of the diameter dxe2x80x2 of a circular laser beam irradiation area (i.e., laser beam spot) 560 and the acceptable placement error range (i.e., tolerance) hxe2x80x2 of a laser beam. In other words, the relationship that xe2x80x9caxe2x80x2=dxe2x80x2+hxe2x80x2xe2x80x9d is established. For example, the diameter dxe2x80x2 of the area or spot 560 is set at 4 xcexcm. The width cxe2x80x2 of the opening 505 is set at, for example, 6 xcexcm. The length gxe2x80x2 of the opening 505 is set at a proper value responsive to the pitch axe2x80x2, the width bxe2x80x2, and the count of the fuses 550.
The fuses 550 are selectively fused and cut by irradiating a laser beam through the opening 505. For example, if the second and fifth fuses 550 that are respectively located at the second and fifth positions from the left-hand side of the opening 505 need to be cut, a laser beam 570 is irradiated to the second fuse 550 and then, it is irradiated to the fifth fuse 550 by way of the opening 505. As a result, as shown in FIG. 3, the parts of the fuses 550 to which the beam 570 has been irradiated are fused and cut.
Generally, after irradiation of a laser beam to a specific part of a repair fuse is completed, the irradiated and fused part of the fuse tends to solidify again, resulting in solid residual parts. Thus, there is a possibility that the residual parts of the repair fuses 550 provided in the prior-art device 500 are in contact with each other, thereby causing short circuit among the fuses 550 thus cut.
Such the short-circuit problem as above can be prevented if the pitch axe2x80x2 of the fuses 550 is increased. In this case, however, there arises a problem that the occupation area of the fuses 550 (i.e., the fuse occupation area) tends to be wider.
To prevent the problem relating to short circuit among the residual parts of the fuses, some techniques have been developed and disclosed. An example of these techniques is disclosed in the Japanese Non-Examined Patent Publication No. 6-120349 published in 1994. In the technique disclosed, the irradiation position of a laser beam onto each repair fuse is alternately shifted in the longitudinal direction of the fuses.
By the way, in recent years, there is a growing trend to further reduce the chip size and to integrate more electronic elements, which requires making the fuse occupation area as small as possible. To meet the requirement, there are ways to reduce the dimension of the fuses themselves and to narrow the pitch of the fuses. However, these two ways will cause other problems as explained below.
Specifically, if the fuses 550 are miniaturized in the prior-art semiconductor device 500, the width bxe2x80x2 of the fuses 550 decreases and as a result, the energy absorbing efficiency or rate of the fuses 550 from the laser beam 570 declines. Thus, to ensure fusing and cut of the fuses 550, the spot diameter dxe2x80x2 of the beam 570 needs to be expanded and at the same time, the energy of the beam 570 needs to be raised. In this case, however, there arises a problem that the fuses 550 are broken or damaged at unwanted positions other than the irradiated parts, damaging the device 500 itself. Accordingly, it is difficult or unable to reduce the fuse occupation area by miniaturization of the fuses 550.
If the pitch axe2x80x2 of the fuses 550 is decreased instead, there arises a problem that the unwanted, adjacent fuses 550 are fused and cut in error. To solve this problem, various techniques that decrease the pitch axe2x80x2 without the cutting or fusing error of the fuses 550 have been developed and proposed.
For example, the Japanese Non-Examined Patent Publication No. 7-273200 published in 1995 discloses a semiconductor device with fuses. In the device, a reflection plate for reflecting a laser beam is provided so as to cover the fuses. The plate has irradiation windows that expose specific irradiation areas of the respective fuses. The windows for the adjoining fuses are alternately shifted in position along the longitudinal direction of the fuses.
The Japanese Non-Examined Patent Publication No. 5-29467 published in 1993 discloses a fuse for redundant circuits, in which a laser beam irradiation window is provided to cover the fuses. The window is formed continuously in a zigzag shape.
The techniques disclosed in the Publication Nos. 7-273200 and 5-29467 are able to decrease the pitch of the fuses. However, the technique disclosed in the Publication No. 7-273200 necessitates an additional process step of providing the reflection plate. As a result, it has a problem that the fabrication cost of a semiconductor device is raised.
On the other hand, the technique disclosed in the Publication No. 5-29467 requires a layer reflecting a laser beam for shielding the peripheral area of the laser beam irradiation window against the beam. Thus, there is a problem of raising the fabrication cost similar to the technique disclosed in the Publication No. 7-273200.
Accordingly, an object of the present invention is to provide a semiconductor device with repair fuses and a laser trimming method therefor that decrease the fuse pitch without short circuit among the adjoining repair fuses and damage to the semiconductor device itself.
Another object of the present invention is to provide a semiconductor device with repair fuses and a laser trimming method therefor that decrease the fuse occupation area without short circuit among the adjoining repair fuses and damage to the semiconductor device itself.
Still another object of the present invention is to provide semiconductor device with repair fuses and a laser trimming method therefor that decrease the fuse pitch and the fuse occupation area without increasing the fabrication cost of the semiconductor device.
The above objects together with others not specifically mentioned will become clear to those skilled in the art from the following description.
According to a first aspect of the present invention, a semiconductor device is provided, which comprises:
(a) a semiconductor substrate;
(b) elongated repair fuses formed on the substrate;
the fuses being arranged in substantially parallel to each other at a pitch a;
each of the fuses having a width b;
(c) a layer formed to cover the fuses;
the layer having an opening that exposes the fuses and that allows the fuses to receive a laser beam from the outside;
the beam having a placement tolerance h for each of the fuses in the opening;
the beam being designed to form an irradiation area with a diameter d for each of the fuses in the opening;
the irradiation area for each of the fuses being arranged along a virtual zigzag shape in the opening; and
(d) a relationship of   d  ≥  a  ≥      (                            b          +          d                2            +      h        )  
xe2x80x83is established among the pitch a, the width b, and the placement tolerance h.
With the semiconductor device according to the first aspect of the invention, the pitch a and the width b of the fuses are determined so as to satisfy the above-described relationship and at the same time, the laser beam is irradiated to the fuses as necessary in such a way that the irradiation areas for the fuses are arranged along the virtual zigzag shape in the opening of the layer that covers the fuses. Thus, the pitch a of the fuses is set to be equal to or smaller than the diameter d of the irradiation areas of the laser beam. Also, the irradiation area for the desired or target fuse is not overlapped with the adjoining fuses to the target fuse, which means that the semiconductor device itself is not damaged due to irradiation overlapping of the laser beam.
As a result, the pitch a of the fuses can be reduced without short circuit among the adjoining fuses and damage to the semiconductor device itself. Due to the reduction of the pitch a, the occupation area of the fuses can be decreased, which is also realized without short circuit among the adjoining fuses and damage to the device itself.
Moreover, the reflection plate and the reflection layer used in the prior-art techniques in the Japanese Non-Examined Patent Publication Nos. 7-273200 and 5-29467 are not necessary in the semiconductor device according to the first aspect of the invention. Accordingly, the pitch a can be decreased without increasing the fabrication cost of the device.
Additionally, as described previously, the Japanese Non-Examined Patent Publication No. 6-120349 discloses the technique that the irradiation position of a laser beam onto each repair fuse is alternately shifted in the longitudinal direction of the fuses. However, the technique in the Publication No. 6-120349 intends only to prevent short circuit among the adjoining fuses. Accordingly, this technique is clearly different from the device according to the first aspect of the invention that aims at reduction of the fuse occupation area through fuse pitch decrease.
In a preferred embodiment of the device according to the first aspect of the invention, each of the fuses has a reference point at a middle point of its exposed part from the opening. Each of the irradiation areas is located in such a way that a center of the area has an offset distance e from the reference point of the corresponding fuse. The offset distance e satisfies the relationship of
xe2x80x832exe2x89xa7{square root over (d2xe2x88x92a2+L )}.
In this embodiment, it is preferred that the opening of the layer is substantially rectangular.
In another preferred embodiment of the device according to the first aspect of the invention, the opening of the layer has a substantially rectangular shape with a length c along the fuses and a width g perpendicular to the fuses. The length c is approximately equal to or less than (1.87xc3x97d).
According to a second aspect of the present invention, another semiconductor device is provided, which comprises:
(a) a semiconductor substrate;
(b) elongated repair fuses formed on the substrate;
the fuses being arranged in substantially parallel to each other at a pitch a;
each of the fuses having a width b;
(c) a layer formed to cover the fuses;
the layer having an opening that exposes the fuses and that allows the fuses to receive a laser beam from the outside;
the beam having a placement tolerance h for each of the fuses in the opening;
the beam being designed to form a first irradiation area and a second irradiation area apart from each other for each of the fuses in the opening;
each of the first irradiation areas and each of the second irradiation areas having an equal diameter d;
the first irradiation area for each of the fuses being arranged along a first virtual zigzag shape and the second irradiation area for each of the fuses being arranged along a second virtual zigzag shape in the opening; and
(d) a relationship of   d  ≥  a  ≥      (                            b          +          d                2            +      h        )  
xe2x80x83is established among the pitch a, the width b, and the placement tolerance h.
With the semiconductor device according to the second aspect of the invention, it is obvious clear that approximately the same advantages as those in the semiconductor device according to the first aspect are present. There is an additional advantage that cutting of the specified or wanted fuses can be ensured and that the fusing and cutting of the fuses can be realized at a high rate even if the fuses are difficult to be cut.
In a preferred embodiment of the device according to the second aspect of the invention, each of the fuses has a reference point at a middle point of its exposed part from the opening. Each of the first irradiation areas is located in such a way that a center of the first irradiation area has a first offset distance e from the reference point of the corresponding fuse. Each of the second irradiation areas is located in such a way that a center of the second irradiation area has a second offset distance f from the reference point of the corresponding fuse. The first offset distance e satisfies the relationship of
2exe2x89xa7{square root over (d2xe2x88x92a2+L )}.
The second offset distance f satisfies a relationship of f=nxc3x97e, where n is a positive constant.
In this embodiment, it is preferred that the opening of the layer is substantially rectangular.
In another preferred embodiment of the device according to the second aspect of the invention, the opening of the layer has a substantially rectangular shape with a length c along the fuses and a width g perpendicular to the fuses. The length c is approximately equal to or less than (3.73xc3x97d).
According to a third aspect of the present invention, a laser trimming method of a semiconductor device is provided, in which the device comprises
(i) a semiconductor substrate;
(ii) elongated repair fuses formed on the substrate;
the fuses being arranged in substantially parallel to each other at a pitch a;
each of the fuses having a width b; and
(iii) a layer formed to cover the fuses;
the layer having an opening that exposes the fuses.
The method comprises the steps of successively irradiating a laser beam to the respective fuses at a placement tolerance h, thereby forming irradiation areas with an equal diameter d for the respective fuses in the opening.
The beam is moved so as to arrange the irradiation areas for the respective fuses along a virtual zigzag shape in the opening while the pitch a, the width b, and the placement tolerance h satisfy a relationship of   d  ≥  a  ≥            (                                    b            +            d                    2                +        h            )        .  
With the laser trimming method of a semiconductor device according to the third aspect of the invention, because of the same reason as described in the device according to the first aspect, approximately the same advantages as those in the device according to the first aspect are given.
In a preferred embodiment of the method according to the third aspect of the invention, each of the fuses has a reference point at a middle point of its exposed part from the opening. Each of the irradiation areas is located in such a way that a center of the area has an offset distance e from the reference point of the corresponding fuse. The offset distance e satisfies the relationship of
2exe2x89xa7{square root over (d2xe2x88x92a2+L )}.
In this embodiment, it is preferred that the opening of the layer is substantially rectangular.
In another preferred embodiment of the method according to the third aspect of the invention, the opening of the layer has a substantially rectangular shape with a length c along the fuses and a width g perpendicular to the fuses. The length c is approximately equal to or less than (1.87xc3x97d).
According to a fourth aspect of the present invention, another laser trimming method of a semiconductor device is provided, in which the device comprises
(i) a semiconductor substrate;
(ii) elongated repair fuses formed on the substrate;
the fuses being arranged in substantially parallel to each other at a pitch a;
each of the fuses having a width b; and
(iii) a layer formed to cover the fuses;
the layer having an opening that exposes the fuses.
The method comprises the steps of successively irradiating a laser beam to the respective fuses at a placement tolerance h, thereby forming a first irradiation area and a second irradiation area with an equal diameter d for each of the fuses in the opening. The first irradiation areas and the second irradiation areas are apart from each other on each of the fuses.
The beam is moved so as to arrange the first irradiation area for each of the fuses along a first virtual zigzag shape and the second irradiation area for each of the fuses along a second virtual zigzag shape in the opening while the pitch a, the width b, and the placement tolerance h satisfy a relationship of   d  ≥  a  ≥            (                                    b            +            d                    2                +        h            )        .  
With the laser trimming method of a semiconductor device according to the fourth aspect of the invention, because of the same reason as described in the device according to the second aspect, approximately the same advantages as those in the device according to the second aspect are given.
In a preferred embodiment of the method according to the fourth aspect of the invention, each of the fuses has a reference point at a middle point of its exposed part from the opening. Each of the first irradiation areas is located in such a way that a center of the first irradiation area has a first offset distance e from the reference point of the corresponding fuse. Each of the second irradiation areas is located in such a way that a center of the second irradiation area has a second offset distance f from the reference point of the corresponding fuse. The first offset distance e satisfies the relationship of
2exe2x89xa7{square root over (d2xe2x88x92a2+L )}.
The second offset distance f satisfies a relationship of f=nxc3x97e, where n is a positive constant.
In this embodiment, it is preferred that the opening of the layer is substantially rectangular.
In another preferred embodiment of the method according to the fourth aspect of the invention, the opening of the layer has a substantially rectangular shape with a length c along the fuses and a width g perpendicular to the fuses. The length c is approximately equal to or less than (3.73xc3x97d).